1. Field of the Invention
The present invention relates to a sensor for Mask Read Only Memory (Mask ROM), and more particularly to a multilevel cell memory (MLC) sensor for Mask Read Only Memory.
2. Description of the Prior Art
Mask Read Only Memory (Mask ROM) generally comprises a plurality of cell transistors. Each cell transistor is used as a memory unit. When programming is required, ions are implanted into the channel area of selected memory cells in order to adjust the threshold voltage of the memory cell. Therefore, On and Off statuses of each of memory cell are set. Generally speaking, whenever a word line (WL) passes through a bit line (BL), a memory cell is built. The memory cell is formed in the covered area of the word line between two adjacent bit lines. Each memory cell can store two bit data by “0” or “1” logic levels, depending on whether the doping is implanted into the channel area of memory cell or not.
A multilevel cell memory is comprised of multilevel cells, each of which is able to store multiple charge states. Each charge state is associated with a memory element bit pattern. For example, the memory element bit pattern “00” is associated with level 3, the memory element bit pattern “10” is associated with level 2, the memory element bit pattern “01” is associated with level 1, and the memory element bit pattern “11” is associated with level 0.
However, when Mask ROM is involved in deep sub-micro semiconductor processing, the integration of the IC tends to be higher and the size of the semiconductor device tends to be smaller. When ions are implanted into the channel area of selected memory cell, the location of the doping area may not be aligned and the threshold voltage of the transistor may be shifted. Parasitic resistance and substrate effects of the bit line may cause memory cell reading the current variation.